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Xilinx FPGA Evaluation Board
IP Core for Xilinx FPGA>> 
 
 DFI Compatible DDR2 SDRAM PHY Design
(Verilog HDL) for Virtex-5

Denali Software, Inc. and Tokyo Electron Device, Ltd. Jointly Developed
DFI Compatible "DDR2 SDRAM PHY Design" for Xilinx FPGA.


The release of DDR2 SDRAM PHY helps to develop LSI with less risk using a high-speed DDR2 interface, relieving developers of time-consuming development and integration tasks needed for special designing of the DDR memory controller.

Combining DDR2 SDRAM PHY, Denali's memory controller design IP "Databahn" featuring technology proven in LSI implementation and inrevium's "Virtex-5 Multi-Application Evaluation Platform (TB-5V-LX110/220/330-DDR2)," developers can effectively improve the time-to-market cycle.

For more information about "Databahn"

For more information about "Virtex-5 Multi-Application Evaluation Platform

About DDR PHY Interface

The goal of the DFI specification is to define a common interface between memory controller logic and DDR PHY interface to reduce cost and time-to-market while increasing the potential for reusing the individual components that compose the memory system.

The DFI specification is being developed by expert contributors from recognized leaders in the semiconductor, IP, and electronic design automation (EDA) industries including ARM, Denali, Intel, Rambus, Samsung, and Synopsys.

DFI Specification Rev 1.0 was released for production development in January 2007 and is available online at: http://www.ddr-phy.org.



Advantages of DFI

Significantly reduces memory controller design work
-Relieves developers of time-consuming work such as development and integration
-Verification tasks can easily be classified
-Commercial IP compatible with DFI can be used
Enables ASIC/FPGA vendor selection
-Increases vendor options
-Reduces integration work specific to a vendor
-Reduces load in reusing design
Seamless integration from FPGA prototype to ASIC
-Accelerates design process
-Reduces risk factors

For more information contact:
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